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rev. prb information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. ADUC842 microconverter ? , 12- bit adcs and dacs with embedded hi-speed 62kb flash mcu one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2003 preliminary technical data

ADUC842 features pin compatable upgrade to aduc812/aduc832 increased performance single cycle 16mips 8052 core high speed 400ksps 12-bit adc increased memory 62kbytes on-chip flash/ee program memory 4kbytes on-chip flash/ee data memory in circuit re-programmable flash/ee, 100 yr retention, 100 kcycles endurance 2304 bytes on-chip data ram smaller package available in 8mm x 8mm chip scale package also available in 52 pin pqfp - pin compatable with aduc812/aduc831 analog i/o 8-channel, 400ksps high accuracy, 12-bit adc on-chip, 20 ppm/ o c voltage reference dma controller, high-speed adc-to-ram capture two 12-bit voltage output dacs dual output pwm- dacs on-chip temperature monitor function 8051 based core 8051-compatible instruction set (16.7 mhz max) high performance single cycle core* 32khz ext crystal,on-chip programmable-pll 12 interrupt sources, two priority levels dual data pointers, extended 11-bit stack pointer on-chip peripherals time interval counter (tic) uart, i2c and spi ? serial i/o watchdog timer (wdt), power supply monitor (psm) power normal: 6ma @ 5 v (core clk = 2.098 mhz) power-down: 15 a @ 3 v development tools low cost, comprehensive development system incorporating non-intrusive single pin emulation ide based, assembly and c source debug applications optical networking - laser power control basestation systems precision instrumentation, smart sensors transient capture systems das and communications systems microconverter is a registered trademark of analog devices, inc. spi is a registered trademark of motorola inc. * 68% of insturctions completed in one or two clock cycles functional block diagram general description the ADUC842 is a complete smart transducer front-end, inte- grating a high-performance self calibrating multichannel adc, dual dac and an optimized single cycle 16mhz 8-bit mcu(8051 instruction set compatible) on a single chip. the device operates from a 32 khz crystal with an on-chip pll generating a high-frequency clock of 16.77mhz. this clock is, in turn, routed through a programmable clock divider from which the mcu core clock operating frequency is generated. the microcontroller is an optimized 8052 core offering up to 16 mips peak performance. 62 kbytes of nonvolatile flash/ee program memory are provided on-chip. 4 kbytes of nonvolatile flash/ee data memory, 256 bytes ram and 2 kbytes of ex- tended ram are also integrated on-chip. the ADUC842 also incorporates additional analog functionality with two 12-bit dacs, power supply monitor, and a bandgap reference. on-chip digital peripherals include two 16-bit ? dacs, dual output 16-bit pwm, watchdog timer, time interval counter, three timers/counters, and three serial i/o ports (spi, i2c and uart). on the aduc812 and aduc832 the i2c and spi interfaces shared some of the same pins. for backwards compatability this is also the case for the ADUC842. however, there is also the option to allow spi operate separately on p3.3, p3.4 and p3.5 while i2c uses the standard pins. the i2c interface has also been enhanced to offer repeated start, general call and quad addressing. on-chip factory firmware supports in-circuit serial download and debug modes (via uart), as well as single-pin emulation mode via the ea pin. a functional block diagram of the ADUC842 is shown above. the part is specified for 3v and 5v operation with a maximum operating frequency of 16.777mhz. 12-bit dac bu f dac 62 kbytes flash/ee program memory 4kbytes flash/eedata memory 2304 bytes user ram 3 16 bit timers 1 real time clock 4 parallel ports 16 mip s 8 0 51 -b as e d mc u w i t h ad d it io na l pe rip her al s pow er s up pl y m on watchdog timer u a rt , i2 c an d spi s eria l i/o ADUC842 xt al 2 xtal1 tem p sensor vr e f inte rnal ba n dg ap vref adc0 adc1 . . . adc5 adc6 adc7 400 ksps 12 -b it a d c mu x osc mu x 16- bit pwm t/h 16-bit ? dac 16- bit ? dac 16- bit pwm pwm0 pw m1 12-bit dac bu f dac hardware calibration pll
rev. prb ?2? ADUC842?specifications 1

parameter v dd = 5 v v dd = 3 v unit test conditions/comments adc channel specifications dc accuracy 2,3 f sample = 147 khz, resolution 12 12 bits integral nonlinearity 1 1 lsb max 2.5v internal reference 0.3 0.3 lsb typ differential nonlinearity 0.9 0.9 lsb max 2.5v internal reference 0.25 0.25 lsb typ integral nonlinearity 9 1.5 1.5 lsb max 1v e xternal reference differential nonlinearity 9 +1.5/-0.9 +1.5/-0.9 lsb max 1v e xternal reference code distrbution 1 1 lsb typ adc input is a dc voltage calibrated endpoint errors 4,5 offset error 2 3 lsb max offset error match 1 1 lsb typ gain error 2 3 lsb max gain error match ?85 ?85 db typ dynamic performance f in = 10 khz sine wave f sample = 147 khz signal-to-noise ratio (snr) 6 71 71 db typ total harmonic distortion (thd) ?85 ?85 db typ peak harmonic or spurious noise ?85 ?85 db typ channel-to-channel crosstalk 7 ?80 ?80 db typ analog input input voltage ranges 0 to v ref 0 to v ref volts leakage current 1 1 a max input capacitance 32 32 pf typ temperature sensor 8 voltage output at 25c 650 650 mv typ voltage tc ?2.0 ?2.0 mv/c typ accuracy 3 3 c typ internal 2.5v v ref accuracy 1.5 1.5 c typ external 2.5v v ref dac channel specifications dac load to agnd internal buffer enabled r l = 10k c l = 100 pf dc accuracy 10 resolution 12 12 bits relative accuracy 3 3 lsb typ differential nonlinearity 11 -1 -1 lsb max guaranteed 12-bit monotonic 1/2 1/2 lsb typ offset error 50 50 mv max v ref range gain error 1 1 % max av dd range 1 1 % typ vref range gain error mismatch 0.5 0.5 % typ % of full-scale on dac1 analog outputs voltage range_0 0 to v ref 0 to v ref v typ dac v ref = 2.5v voltage range_1 0 to v dd 0 to v dd v typ dac v ref = v dd output impedance 0.5 0.5 typ i sink 50 50 a typ dac ac characteristics voltage output settling time 15 15 s typ full-scale settling time to within 1/2 lsb of final value digital-to-analog glitch energy 10 10 nv sec typ 1 lsb change at major carry (av dd = dv dd = 2.7v to 3.3v or 4.5v to 5.5v. v ref = 2.5 v in ternal reference, fcore = 16.777 mhz, all specifications t a = t min to t max , unless otherwise noted.)
rev. prb ?3? ADUC842

parameter v dd = 5 v v dd = 3 v unit test conditions/comments dac channel specifications 12,13 internal buffer disabled dc accuracy 10 resolution 12 12 bits relative accuracy 3 3 lsb typ differential nonlinearity 11 -1 -1 lsb max guaranteed 12-bit monotonic 1/2 1/2 lsb typ offset error 10 10 mv max v ref range gain error 1 1 % typ vref range gain error mismatch 0.5 0.5 % typ % of full-scale on dac1 analog outputs voltage range_0 0 to v ref 0 to v ref v typ dac v ref = 2.5v reference input/output reference ouput 14 output voltage (v ref ) 2.5 2.5 v accuracy 2.5 2.5 % max of v ref measured at the c ref pin power supply rejection 47 57 db typ reference temperature coefficient 20 20 ppm/c typ internal v ref power-on time 80 80 ms typ external refernce input 15 voltage range (v ref ) 9 0.1 0.1 v min v dd v dd v max input impedance 20 20 k typ input leakage 10 10 a max internal band gap deselected via adccon1.6 power supply monitor (psm) dv dd trip point selection range 2.63 vmin four trip points selectable in 4.37 vmax t his range programmed via tpd1?0 in psmcon dv dd power supply trip point accuracy 3.5 % max watch dog timer (wdt) 9 time-out period 0 0 ms min nine time-out periods 2000 2000 ms max. selectable in this range flash/ee memory reliability characteristics 16 endurance 17 100,000 100,000 cycles min data retention 18 100 100 years min digital inputs input high voltage (v inh ) 2.4 v min input low voltage (v inl ) 0.8 v max input leakage current (port 0,1, ea) 10 a max v in = 0 v or v dd 1 1 a typ v in = 0 v or v dd logic 1 input current (all digital inputs) 10 a max v in = v dd 1 1 a typ v in = v dd logic 0 input current (port 2, 3) ?80 a max ?40 ?40 a typ v il = 0 v logic 1-0 transition current (port 2, 3) ?7 0 0 a max v il = 2 v ?400 ?400 a typ v il = 2 v crystal oscillator logic inputs, xtal1 only vinl, input low voltage 0.8 0.4 v typ vinh, input high voltage 3.5 2.5 v typ
rev. prb ?4? ADUC842?specifications 1

parameter v dd =5v v dd =3v units test conditions xtal1 input capacitance 18 18 pf typ xtal2 output capacitance 18 18 pf typ mcu clock rate 16.777216 16.777216 mhz max digital outputs output high voltage (v oh ) 2.4 2.4 v min v dd = 4.5 v to 5.5 v i source = 80 a 4.0 2.6 v typ v dd = 2.7 v to 3.3 v i source = 20 a output low voltage (v ol ) ale, ports 0 and 2 0.4 0.4 v max i sink = 1.6 ma 0.2 0.2 v typ i sink = 1.6 ma port 3 0.4 0.4 vmax i sink = 4 ma sclock/sdata 0.4 0.4 vmax i sink = 8 ma floating state leakage current 10 10 a max 1 1 a typ floating state output capacitance 10 10 pf typ start up time core clk = 16mhz at power-on 500 500 ms typ from idle mode 100 100 s typ from power-down mode wakeup with int0 interrupt 150 400 ms typ wakeup with spi/i 2 c interrupt 150 400 ms typ wakeup with external reset 150 400 ms typ after external reset in normal mode 3 3 ms typ after wdt reset in normal mode 3 3 ms typ con trolled via wdcon sfr power requirements 19,20 power supply voltages av dd / dv dd - agnd 2.7 v min. av dd / dv dd = 3v nom. 3.3 v max. 4.5 v min. av dd / dv dd = 5v nom. 5.5 v max. power supply currents normal mode d vdd current 9 12 6 ma typ fcore = 8 mhz (cd=3) a vdd current 9 1.4 1.4 ma max d vdd current 25 n/a ma max fcore = 16 mhz (cd=0) 21 n/a ma typ a vdd current 1.4 n/a ma max power supply currents idle mode d vdd current 9 5 2.5 ma typ fcore = 8 mhz (cd=3) a vdd current 9 0.11 0.11 ma typ d vdd current 9 11 n/a ma max fcore =16 mhz (cd=0) 10 n/a ma typ a vdd current 9 0.11 n/a ma typ power supply currents power down mode for any core clk a vdd current 3 2.5 ua typ d vdd current 35 15 ua max osc off 25 12 ua typ 120 120 ua typ osc on typical additional power supply currents avdd = dvdd = 5v psm peripheral 50 ua typ adc 1.5 ma typ dac 150 ua typ
rev. prb ?5? ADUC842

notes 1 temperature range -40oc to +85oc. 2 adc linearity is guaranteed during normal microconverter core operation. 3 adc lsb size = vref / 2^12 i.e for internal vref=2.5v, 1lsb = 610uv and for external vref =1v, 1lsb = 244uv. 4 offset and gain error and offset and gain error match are measured after factory calibration. 5 based on external adc system components the user may need to execute a system calibration to remove additional external channel errors and achieve these specifications. 6 snr calculation includes distortion and noise components. 7 channel to channel crosstalk is measured on adjacent channels. 8 the temperature monitor will give a measure of the die temperature directly, air temperature can be inferred from this result. 9 these numbers are not production tested but are guaranteed by design and/or characterization data on production release. 10 dac linearity is calculated using : reduced code range of 48 to 4095, 0 to vref range. reduced code range of 48 to 3945, 0 to v dd range. dac output load = 10k ohms and 100 pf. 11 dac differential nonlinearity specified on 0 to vref and 0 to vdd ranges 12 dac specification for output impedance in the unbuffered case depends on dac code 13 dac specifications for isink, voltage output settling time and digital-to-analog glitch engergy depend on external buffer imp lementation in unbuffered mode. 14 measured with vref and cref pins decoupled with 0.1f capacitors to graound. power-up time for the internal reference will be d etermined by the value of the decoupling capacitor chosen for both the vref and cref pins. 15 when using an external reference device, the internal bandgap reference input can be bypassed by setting the adccon1.6 bit. in this mode the vref and cref pins need to be shorted together for correct operation. 16 flash/ee memory reliability characteristics apply to both the flash/ee program memory and the flash/ee data memory. 17 endurance is qualified to 100 kcycles as per jedec std. 22 method a117 and measured at -40oc, +25oc, and +85oc, typical enduran ce at 25oc is 700 kcycles. 18 retention lifetime equivalent at junction temperature (tj) = 55oc as per jedec std. 22 method a117. retention lifetime based on an activation energy of 0.6ev will derate with junction temperature as shown in figure 27 in the flash/ee memory description sec tion of this data sheet. 19 power supply current consumption is measured in normal, idle, and power-down modes under the following conditions: normal mode: r eset = 0.4 v, digital i/o pins = open circuit, core clk changed via cd bits in pllcon, core executing internal software loop. idle mode: reset = 0.4 v, digital i/o pins = open circuit, core clk chan ged via cd bits in pllcon, pcon.0=1, core execution suspended in idle mode. power-down mode: reset = 0.4 v, all port 0 pins = 0.4 v, all other digital i/o and port 1 pins are open circuit, core clk changed via cd bits in pllcon, pcon.0=1, core execution suspended inpower-down mode, osc turned on or off via osc_pd bit (pllcon.7) in pllcon sfr 20 d vdd power supply current will increase typically by 3 ma (3 v operation) and 10 ma (5 v operation) during a flash/ee memory progra m or erase cycle. specifications subject to change without notice.
rev.prb ADUC842 ?6?

ordering guide temperature package package model range description option ADUC842bs ?40c to +85c 52-lead plastic quad flatpack s-52 ADUC842bcp ?40c to +85c 56-lead chip scale package cp-56 absolute maximum ratings * (t a = 25c unless otherwise noted) av dd to dv dd . . . . . . . . . . . . . . . . . . ?0.3 v to +0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . ?0.3 v to +0.3 v dv dd to dgnd, av dd to agnd . . . . ?0.3 v to +7 v digital input voltage to dgnd ?0.3 v, dv dd + 0.3 v digital output voltage to dgnd ?0.3 v, dv dd + 0.3 v v ref to agnd . . . . . . . . . . . . . . . ?0.3 v, av dd + 0.3 v analog inputs to agnd . . . . . . . ?0.3 v, av dd + 0.3 v operating temperature range industrial ADUC842bs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c operating temperature range industrial ADUC842bcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c storage temperature range . . . . . . . . ?65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . 150c ja thermal impedance (aduc831bs) . . . . . . . 90c/w ja thermal impedance (aduc831bcp) . . . . . 52c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADUC842 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. prb ADUC842 ?7?

pin function descriptions mnemonic type function dv dd p digital positive supply voltage, 3 v or 5 v nominal av dd p analog positive supply voltage, 3 v or 5 v nominal c ref i decoupling input for on-chip reference. connect 0.1 f between this pin and agnd. v ref i / o reference input/output. this pin is connected to the internal reference through a series resistor and is the reference source for the analog-to-digital converter. the nominal internal reference voltage is 2.5 v and this appears at the pin. this pin can be overdriven by an external reference. agnd g analog ground. ground reference point for the analog circuitry. p1.0?p1.7 i port 1 is an 8-bit input port only. unlike other ports, port 1 defaults to analog input mode, to configure any of these port pins as a digital input, write a ?0? to the port bit. port 1 pins are mul- tifunction and share the following functionality. adc0?adc7 i analog inputs. eight single-ended analog inputs. channel selection is via adccon2 sfr. t 2 i timer 2 digital input. input to timer/counter 2. when enabled, counter 2 is incremented in response to a 1 to 0 transition of the t2 input. t2ex i d igital input. capture/reload trigger for counter 2 and also functions as an up/down control input for counter 2. s s i slave select input for the spi interface sdata i/o user selectable, i 2 c-compatible or spi data input/output pin sclock i/o s erial clock pin for i 2 c-compatible or spi serial interface clock mosi i/o spi master output/slave input data i/o pin for spi interface miso i/o spi master input/slave output data i/o pin for spi serial interface dac0 o voltage output from dac0 dac1 o voltage output from dac1 reset i d igital input. a high level on this pin for 24 master clock cycles while the oscillator is running resets the device. p3.0?p3.7 i/o port 3 is a bid irectional port with internal pull-up resistors. port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. as inputs port 3 pins being pulled externally low will source current because of the internal pull- up resistors. port 3 pins also contain various secondary functions which are described below. pwmc i pwm clock input pwm0 o pmw0 voltage output. pwm outputs can be configured to use ports 2.6 & 2.7 or 3.4 and 3.3 pwm1 o pmw1 voltage ouput. see cfg832 register for further information. rxd i/o receiver data input (asynchronous) or data input/output (synchronous) of serial (uart) port t x d o transmitter data output (asynchronous) or clock output (synchronous) of serial (uart) port int0 i interrupt 0, programmable edge or level triggered interrupt input, which can be programmed to one of two priority levels. this pin can also be used as a gate control input to timer 0. int1 i interrupt 1, programmable edge or level triggered interrupt input, which can be programmed to one of two priority levels. this pin can also be used as a gate control input to timer 1. t0 i timer/counter 0 input t1 i timer/counter 1 input convst i active low convert start logic input for the adc block when the external convert start function is enabled. a low-to-high transition on this input puts the track/hold into its hold mode and starts conversion. w r o write control signal, logic output. latches the data byte from port 0 into the external data memory. r d o read control signal, logic output. enables the external data memory to port 0. xtal2 o output of the inverting oscillator amplifier xtal1 i i nput to the inverting oscillator amplifier and input to the internal clock generator circuits. dgnd g digital ground. ground reference point for the digital circuitry. p2.0?p2.7 i/o port 2 is a bid irectional port with internal pull-up resistors. port 2 pins that have 1s written to them are (a8?a15) pulled high by the internal pull-up resistors, and in that state they can be used as inputs. as inputs port 2 (a16?a23) pins being pulled externally low will source current because of the internal pull-up resistors. port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space.
rev.prb ADUC842 ?8?

mnemonic type function psen o program store enable, logic output. this output is a control signal that enables the external program memory to the bus during external fetch operations. it is active every six oscillator periods except during external data memory accesses. this pin remains high during internal program execution. psen can also be used to enable serial download mode when pulled low through a resistor on power-up or reset. a l e o address latch enable, logic output. this output is used to latch the low byte (and page byte for 24-bit address space accesses) of the address into external memory during normal operation. e a i external access enable, logic input. when held high, this input enables the device to fetch code from internal program memory locations 0000h to 1fffh. when held low this input enables the device to fetch all instructions from external program memory. this pin should not be left float. p0.7?p0.0 i/o port 0 is an 8-bit open drain bidirectional i/o port. port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs. port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. in this application it uses strong internal pull-ups when emitting 1s. terminology adc specifications integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1/2 lsb below the first code transition and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., +1/2 lsb. gain error this is the deviation of the last code transition from the ideal ain voltage (full scale ? 1.5 lsb) after the offset error has been adjusted out. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise +distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db. total harmonic distortion total harmonic distortion is the ratio of the rms sum of the harmonics to the fundamental. dac specifications relative accuracy relative accuracy or endpoint linearity is a measure of the maxi mum deviation from a straight line passing through the endp oints of the dac transfer function. it is measured after adju sting for zero error and full-scale er- ror. voltage output settling time this is the amount of time it takes for the output to settle to a specified level for a full-scale input change. digital-to-analog glitch impulse this is the amount of charge injected into the analog out- put when the inputs change state. it is specified as the area of the glitch in nv sec. pin function description (continued)
rev. prb ADUC842 ?9?

figure 1 ADUC842 block diagram (shaded areas are features not present on the aduc812) pin configuration 3,1 ,'(17,),(5 723 9,(: 1rw wr 6fdoh 3 $ ' 3 $ ' 3 $ ' 3 $ ' ' 9 ' ' ' * 1 ' 3 $ ' 3 $ ' 3 $ ' 3 $ ' $ / ( 3 6 ( 1 ( $ 3$'&7 3$'&7(; 3$'& 3$'& $9 '' $*1' & 5() 9 5() '$& '$& 3$'& 3$'&66 3$'& 33:0$$ 33:0$$ 3$$ 3$$ '*1' '9 '' ;7$/ ;7$/ 3$$ 3$$ 3$$ 3$$ 6'$7$026, 3 $ ' & 5 ( 6 ( 7 3 5 [ ' 3 7 [ ' 3 , 1 7 3 , 1 7 0 , 6 2 3 : 0 ' 9 ' ' ' * 1 ' 3 7 3 : 0 & 3 : 0 ( ; 7 & / . 3 7 & 2 1 9 6 7 3 5 ' 6 & / 2 & . 3 : 5 $'x&3,134)3 3$'&7(; s$'& 3$'& $9'' $9'' $*1' $*1' $*1' &uhi 9uhi '$& '$& 3$'& 3$'&66 3 $ ' & 3 $ ' & 5 ( 6 ( 7 3 5 ; ' 3 7 ; ' 3 , 1 7 0 , 6 2 3 : 0 3 , 1 7 ' 9 g g ' * q g 3 7 3 : 0 & 3 : 0 ( ; 7 & / . 3 7 & 2 1 9 6 7 3 : 5 3 5 ' 6 & / 2 & . 33:0$$ 33:0$$ 3$$ 3$$ '*1' '*1' '9'' ;7$/ 3$$ 3$$ 3$$ 3$$ 6'$7$026, 3 $ ' & 7 3 $ ' 3 $ ' 3 $ ' 3 $ ' ' 9 g g ' * q g 3 $ ' 3 $ ' 3 $ ' 3 $ ' $ / ( 3 6 ( 1 ( $ 3,1 ,'(17,),(5 $'x&3,1&63 723 9,( : 1rw wr 6fdoh ;7$/ watchdog timer 256 bytes user ram power supply monitor temp sensor bandgap reference a v d d a g n d d v d d d v d d d v d d d g n d d g n d d g n d r e s e t 325 s d a t a / m o s i m i s o 6 6 x t a l 1 ADUC842 adc control and calibration dac1 dac control 12-bit voltage output dac t0 t1 t2ex t2 ,17 ,17 ( $ 3 6 ( 1 a l e s i n g l e - p i n e m u l a t o r t x d r x d 4kbytesdata flash/ee 62 kbytes program flash/ee including user download mode asynchronous serial port (uart) 16mips 8052 mcu core downloader debugger synchronous serial interface (spi or i2c ) 16-bit counter timers time interval counter (wakeup cct) x t a l 2 osc 2kbytesuserxram 2 x data pointers 11-bit stack pointer 12-bit voltage output dac 0x[ %lw $'& $'& $'& $'& $'& dac0 mux 16-bit dac pwm0 pwm1 16-bit pwm 16-bit pwm pwm control 16-bit 4% dac 7+ 9 5() & 5() %8) uart timer prog. clock divider pll s c l o c k
rev.prb ADUC842 ?10?

introduction the ADUC842 is a 16mips 8052 core upgrade to the aduc832. it has all the same features as the aduc832 but the standard 12-cycle 8052 core has been replaced with a 16mips single cycle core. since the ADUC842 and aduc832 share the same feature set only the differneces bettween the two chips are docu- mented here. for full documentation on the aduc832 please consult the datasheet available at http://www.analog.com/microconverter 8052 instruction set the following pages document the number of clock cycles required for each instruction. most instructions are ex- ecuted in one or two clock cycles resulting in a 16mips peak peformance when operating at pllcon = 00h. timer operation timers on a standard 8052 increment by one with each machine cycle. on the ADUC842 one machine cycle is equal to one clock cycle hence the timers will increment at the same rate as the core clock. ale the output on the ale pin on the aduc832 was a clock at 1/6th of the core operating frequency. on the ADUC842 the ale pin operates as follows. for a single machine cycle instruction: ale is high for the first half of the machine cycle and low for the second half. the ale output is at the core operating frequency. for a two or more machine cycle instruction: ale is high for the first half of the first machine cycle and then low for the rest of the machine cycles. external memory access there is no support for external program memory access on the ADUC842. when accessing external ram the ewait register may need to be programmed in order to give extra machine cycles to movx commands. this is to account for differing external ram access speeds. baud rate generation there is an addition divide by two in the fractional divider of the ADUC842 this means that any values calculated for t3con for the aduc832 need to be incremented by one in order to give the same baud rate on the ADUC842.
rev. prb ADUC842 ?11?

instruction table mnemonic description bytes cycles arithmetic add a,rn add register to a 1 1 add a,@ri add indirect memory to a 1 2 add a,dir add direct byte to a 2 2 add a,#data add immediate to a 2 2 addc a,rn add register to a with carry 1 1 addc a,@ri add indirect memory to a with carry 1 2 addc a,dir add d irect byte to a with carray 2 2 add a,#data add immediate to a with carry 2 2 subb a,rn subtract register from a with borrow 1 1 subb a,@ri subtract indirect memory from a with borrow 1 2 subb a,dir subtract direct from a with borrow 2 2 subb a,#data subtract immediate from a with borrow 2 2 inc a in crement a 1 1 inc rn increment register 1 1 inc @ri increment indirect memory 1 2 inc dir increment direct byte 2 2 inc dptr increment data pointer 1 3 dec a decrement a 1 1 dec rn decrement register 1 1 dec @ri d ecrement indirect memory 1 2 dec dir decrement direct byte 2 2 mul ab multiply a by b 1 9 div ab divide a by b 1 9 da a decimal adjust a 1 2 logic anl a,rn and register to a 1 1 anl a,@ri and indirect memory to a 1 2 anl a,dir and direct byte to a 2 2 anl a,#data and immediate to a 2 2 anl dir,a and a to direct byte 2 2 anl dir,#data and immediate data to direct byte 3 3 orl a,rn or register to a 1 1 orl a,@ri or indirect memory to a 1 2 orl a,dir or direct byte to a 2 2 orl a,#data or immediate to a 2 2 orl dir,a or a to direct byte 2 2 orl dir,#data or imm ediate data to direct byte 3 3
rev.prb ADUC842 ?12?

xrl a,rn exclusive-or register to a 1 1 xrl a,@ri exclusive-or indirect memory to a 2 2 xrl a,#data exclusive-or immediate to a 2 2 xrl dir,a exclusive-or a to direct byte 2 2 xrl a,dir exclusive-or indirect memory to a 2 2 xrl dir,#data exclusive-or immediate data to direct 3 3 clr a clear a 1 1 cpl a com plement a 1 1 swap a swap nibb les of a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 data transfer mov a,rn move register to a 1 1 mov a,@ri move indirect memory to a 1 2 mov rn,a move a to register 1 1 mov @ri,a move a to indirect memory 1 2 mov a,dir move direct byte to a 2 2 mov a,#data move immediate to a 2 2 mov rn,#data move register to immediate 2 2 mov dir,a move a to direct byte 2 2 mov rn, dir mov register to direct byte 2 2 mov dir, rn move direct to register 2 2 mov @ri,#data move immediate to indirect memory 2 2 mov dir,dir m ove direct byte to direct byte 3 3 mov dir,#data m ove immediate to direct byte 3 3 mov dptr,#data move immediate to data pointer 3 3 movc a,@a+dptr move code byte relative dptr to a 1 4 movc a,@a+pc move code byte relative pc to a 1 4 movx a,@ri move external (a8) data to a 1 4 movx a,@dptr move ex ternal (a16) data to a 1 4 movx @ri,a move a to external data (a8) 1 4 movx @dptr,a move a to external data (a16) 1 4 push dir push direct byte onto stack 2 2 pop dir pop direct byte from stack 2 2 xch a,rn exchange a and register 1 1 xch a,@ri exchange a and indirect memory 1 2 xchd a,@ri exchange a and indirect memory nibble 1 2 xch a,dir exchange a and direct byte 2 2 boolean
rev. prb ADUC842 ?13?

clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c,bit and direct bit and carry 2 2 anl c,/bit and direct bit inverse to carry 2 2 orl c,bit or direct bit and carry 2 2 orl c,/bit or direct bit inverse to carry 2 2 mov c,bit m ove direct bit to carry 2 2 mov bit,c m ove carry to direct bit 2 2 branching jmp @a+dptr jump indirect relative to dptr 1 3 ret return from subroutine 1 4 reti ret urn from interrupt 1 4 acall addr11 absolute jump to subroutine 2 3 ajmp addr11 absolute jump unconditional 2 3 sjmp rel short jump (relative address) 2 3 jc rel jump on carry = 1 2 3 jnc rel jump on carry = 0 2 3 jz rel jump on accumulator = 0 2 3 jnz rel j ump on accumulator != 0 2 3 djnz rn,rel decrement register, jnz relative 2 3 ljmp long jump unconditional 3 4 lcall addr16 long jump to subroutine 3 4 jb bit,rel jump on direct bit = 1 3 4 jnb bit,rel jump on direct bit = 0 3 4 jbc bit,rel jump on direct bit = 1 and clear 3 4 cjne a,dir,rel compare a, direct jne relative 3 4 cjne a,#data,rel compare a, immediate jne relative 3 4 cjne rn,#data,rel compare register, immediate jne relative 3 4 cjne @ri,#data,rel compare indirect, immediate jne relative 3 4 djnz dir,rel decrement direct byte, jnz relative 3 4 miscellaneous nop no operation 1 1 notes: 1. one cycle is one clock. 2. cycles of movx instructions are 4 cycles when they have 0 wait state. cycles of movx instructions are 4+n cycles when they have n wait states. 3. cycles of lcall instruction are 3 cycles when the lcall instruction comes from interrupt.
rev.prb ADUC842 ?14?

i 2 c-compatible interface the ADUC842 supports a fully licensed * i 2 c serial interface. the i 2 c interface is implemented as a full hardware slave and software master. sdata is the data i/o pin and sclock is the serial clock. these two pins are shared with the mosi and sclock pins of the on-chip spi interface. to enable the i2c interface the spi interface must be turned off (see spe in spicon previously) or the spi interface must be moved to p3.3, p3.4 and p3.5 via the cfg841.1 bit. application note uc001 describes the operation of this interface as implemented is available from the microconverter website at www.analog.com/ microconverter. three sfrs are used to control the i 2 c interface. these are described below: i2ccon: i 2 c control register sfr address e8h power-on default value 00h bit addressable yes table i2ccon sfr bit designations master mode bit name description 7 mdo i 2 c software master data output bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. data written to this bit will be outputted on the sdata pin if the data output enable (mde) bit is set. 6 mde i 2 c software master data output enable bit (master mode only). set by user to enable the sdata pin as an output (tx). cleared by the user to enable sdata pin as an input (rx). 5 mco i 2 c software master clock output bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. data written to this bit will be outputted on the sclock pin. 4 mdi i 2 c software master data input bit (master mode only). this data bit is used to implement a master i 2 c receiver interface in software. data on the sdata pin is latched into this bit on sclock if the data output enable (mde) bit is ?0.? 3 i2cm i 2 c master/slave mode bit. set by user to enable i 2 c software master mode. cleared by user to enable i 2 c hardware slave mode. 2 ---- rsvd 1 ---- rsvd 0 ---- rsvd table i2ccon sfr bit designations slave mode bit name description 7 i2csi i 2 c stop interrupt enable bit. set by the user to enable i2c stop interrupts. if set a stop bit that follows a valid start condition will generate an interrupt. cleared by the user to disable i2c stop interrupts. 6 i2cgc i 2 c general call status bit set by hardware after receiving a general call address. cleared by the user. 5 i2cid1 i 2 c interrupt decode bits. 4 i2cid0 set by hardware to indicate the source of an i2c interrupt 00 start and matching address 01 repeated start and matching address 10 user data 11 stop after a start and matching address 3 i2cm i 2 c master/slave mode bit. set by user to enable i 2 c software master mode. cleared by user to enable i 2 c hardware slave mode. 2 i2crs i 2 c reset bit (slave mode only). set by user to reset the i 2 c interface. cleared by user code for normal i 2 c operation. 1 i2ctx i 2 c direction transfer bit (slave mode only). set by the microconverter if the interface is transmitting.
rev. prb ADUC842 ?15?

cleared by the microconverter if the interface is receiving. 0 i2ci i 2 c interrupt bit (slave mode only). set by the microconverter after a byte has been transmitted or received. cleared automatically when user code reads the i2cdat sfr (see i2cdat below). i2cadd i 2 c address register function h olds the first i 2 c peripheral address for the part. it may be overwritten by user code. technical noteuc001 at www.analog.com/microconverter describes the format of the i 2 c standard 7-bit address in detail. sfr address 9bh power-on default value 55h bit addressable n o i2cadd1 i 2 c address register function holds the second i 2 c peripheral address for the part. it may be overwritten by user code. sfr address 91h power-on default value 00h bit addressable n o i2cadd2 i 2 c address register function holds the third i 2 c peripheral address for the part. it may be overwritten by user code. sfr address 92h power-on default value 00h bit addressable n o i2cadd3 i 2 c address register function holds the fourth i 2 c peripheral address for the part. it may be overwritten by user code. sfr address 93h power-on default value 00h bit addressable n o i2cdat i 2 c data register function the i2cdat sfr is written by the user to transmit data over the i 2 c interface or read by user code to read d ata just received by the i 2 c interface. accessing i2cdat automatically clears any pending i 2 c interrupt and the i2ci bit in the i2c con sfr. user software s hould only access i2cdat once per interrupt cycle. sfr address 9ah power-on default value 00h bit addressable n o * purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i 2 c patent rights to use the ADUC842 in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
rev.prb ADUC842 ?16?

the main features of the microconverter i 2 c interface are: - only two bus lines are required; a serial data line (sdata) and a serial clock line (sclock). - an i 2 c master can communicate with multiple slave devices. because each slave device has a unique 7-bit address then single master/slave relationships can exist at all times even in a multi slave environment - ability to respond to 4 seperate addresses when operat- ing in slave mode - an i 2 c slave can respond to repeated start conditions without a stop bit in between. this allows a master to change direction of transfer without giving up the bus. - on-chip filtering rejects <50ns spikes on the sdata and the sclock lines to preserve data integrity. i 2 c master i 2 c slave#2 i 2 c slave#1 dv dd figure 36. t ypical i 2 c system software master mode the aduc841 can be used as a i 2 c master device by config- uring the i 2 c peripheral in master mode and writing sotware to output the data bit by bit. this is referred to as a software master. master mode is enabled by setting the i2cm bit in the i2ccon register. to transmit data on the sdata line, mde must be set to enable the output driver on the sdata pin. if mde is set then the sdata pin will be pulled high or low depending on whether the mdo bit is set or cleared. mco controls the sclock pin and is always configured as an output in mas- ter mode. in master mode the sclock pin will be pulled high or low depending on the whether mco is set or cleared. to receive data, mde must be cleared to disable the output driver on sdata. software must provide the clocks by tog- gling the mco bit and read sdata pin via the mdi bit. if mde is cleared mdi can be used to read the sdata pin. the value of the sdata pin is latched into mdi on a rising edge pf sclock. mdi is set if the sdata pin was high on the last rising edge of sclock. mdi is clear if the sdata pin was low on the last rising edge of sclock. software must control mdo, mco and mde appropri- ately to generate the start condition, slave address, acknowledge bits, data bytes and stop conditions appro- priately. these functions are provided in tech note uc001. hardware slave mode after reset the ADUC842 defaults to hardware slave mode. the i 2 c interface is enabled by clearing the spe bit in spicon. slave mode is enabled by clearing the i2cm bit in i2ccon. the ADUC842 has a full hardware slave. in slave mode the i 2 c address is stored in the i2cadd regis- ter. data received or to be transmitted is stored in the i2cdat register. once enabled in i 2 c slave mode the slave controller waits for a start condition. if the ADUC842 detects a valid start condition, followed by a valid address, followed by the r/ bit the i2ci interrupt bit will get automatically set by hard- ware. the i 2 c peripheral will only generate a core interrupt if the user has pre-configured the i 2 c interrupt enable bit in the ieip2 sfr as well as the global interrupt bit ea in the ie sfr. i.e. ; enabling i2c interrupts for the aduc831 mov ieip2,#01h ; enable i2c interrupt setb ea on the aduc841 an auto-clear of the i2ci bit is imple- mented so this bit is cleared automatically on a read or write access to the i2cdat sfr. mov i2cdat, a ; i2ci auto-cleared mov a, i2cdat ; i2ci auto-cleared if for any reason the user tries to clear the interrupt more than once i.e. access the data sfr more than once per inter- rupt then the i 2 c controller will halt. the interface will then have to be reset using the i2crs bit. the user can choose to poll the i2ci bit or enable the inter- rupt. in the case of the interrupt the pc counter will vector to 003bh at the end of each complete byte. for the first byte when the user gets to the i2ci isr the 7-bit address and the r/ bit will appear in the i2cdat sfr. the i2ctx bit contains the r/ bit sent from the master. if i2ctx is set then the master would like to receive a byte. hence the slave will transmit data by writing to the i2cdat register. if i2ctx is cleared the master would like to trans- mit a byte. hence the slave will receive a serial byte. software can interrogate the state of i2ctx to determine whether is should write to or read from i2cdat. once the ADUC842 has received a valid address, hardware will hold sclock low until the i2ci bit is cleared by soft- ware. this allows the master to wait for the slave to be ready before transmitting the clocks for the next byte. the i2ci interrupt bit will be set every time a complete data byte is received or transmitted provided it is followed by a valid ack. if the byte is followed by a nack an interrupt is not generated. the ADUC842 will continue to issue inter- rupts for each complete data byte transferred until a stop condition is received or the interface is reset. when a stop condition is received, the interface will reset to a state where it is waiting to be addressed (idle). simi- larly, if the interface receives a nack at the end of a sequence it also returns to the default idle state. the i2crs bit can be used to reset the i 2 c interface. this bit can be used to force the interface back to the default idle state.
rev. prb ADUC842 ?17?

outline dimensions dimensions shown in inches and (mm). 52-lead plastic quad flatpack (s-52) 723 9,(: 3,16 '2:1 3, 1 64 64 %6& 6($7,1* 3/$1( 56lead chip scale package(cp-56) %6& r 0$; 0$; 120 5() 0$; 120 1 14 %27720 9,(: 64 15 28 29 42 43 56 5() 0,1 bsc sq 3,1 ,1',&$725 723 9,(: %6& 64

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